1. Field of the Invention
The present invention relates to a clock frequency multiplier and a method for multiplying a clock frequency. More particularly, the present invention relates to a clock frequency multiplier implemented with a pure digital logic circuit, and a method thereof.
2. Description of the Related Art
Conventionally, a clock frequency multiplier is usually implemented with a phase lock loop (PLL) as the PLL has excellent output quality. However, the PLL includes some analog components (such as an operational amplifier) and some passive components (such as resistors and capacitors). These components occupy a large area of an integrated circuit. Moreover, the components need separate simulation, or even require separate design and layout for different fabrication processes.
However, the superior output quality of the PLL may not be necessary for some integrated circuits as the circuits only need stable frequency multiplication. In such circumstances, it is desirable to have a clock frequency multiplier offering stable frequency multiplication without incurring the problems as mentioned above.